TevenDesign hierarchy
The whole design in the activity bar, expanded level by level, even for big designs. Click an instance to open its module; right-click for Go to Instantiation and Copy Hierarchical Path.
Teven for VS Code · free edition
Find the logic behind every signal.
Teven brings a design browser and simulation debugger for Verilog and SystemVerilog into VS Code. Walk the design hierarchy, double-click a signal to jump to the logic that drives it across any number of levels, and view your simulation's waveforms beside the code.
macOS on Apple silicon (M1 or newer). Linux and Windows are planned.
HIERARCHY
▾ soc_top
▸ u_cpu
▾ u_periph
▸ u_gpio
▸ u_uart
▸ u_timer
▸ u_mem
41 always_ff @(posedge clk_i) begin 42 if (!rst_ni) 43 tx_q <= 1'b1; 44 else if (bit_tick) 45 tx_q <= shift_q[0]; 46 end 47 48 assign tx_o = tx_q;
clk_i
tx_o
What it does
Double-click tracing
Double-click a signal and Teven follows ports up and down the hierarchy to the real
logic, with every driving line selected. Trace drivers or loads, down to single bits
(x[3]) and struct fields.
Signals window
Every signal of the selected instance: direction, type, width, driver and load counts, and remarks such as undriven, multi-driven or unloaded. Filter it, sort it, trace from it.
Compile and elaborate
Point Teven at a filelist (.f), files or folders. Each file is syntax-checked
with errors in Problems, then Elaborate builds the design database. Change a file
and Re-elaborate rebuilds it, keeping your place.
Waveforms
Open a VCD or FST dump and it shows in Teven's waveform viewer: zoom, cursors and markers, radix, groups, and a saved setup to come back to.
Made for RTL
Verilog and SystemVerilog syntax highlighting in dark and light themes, code folding, clickable signals and parameters, and dimmed port names in connections.
Your design stays on your computer
Teven reads your RTL, filelists and waveforms on your own machine and builds its database there. It does not send your files or their contents anywhere, and it collects no telemetry. Nothing else needs installing: the extension brings everything it uses, so you don't need Python.
Get started in five steps
- Install Teven from the Extensions view in VS Code (search for “Teven”), and open the folder that has your RTL.
- Click the Teven icon in the activity bar.
- Choose Compile Files or Filelist… and pick your filelist or your
.sv/.vfiles. - Choose Elaborate and type the top module. The database (
.ddb) is built and opened, and reopened next time. - Expand the hierarchy, open a module and double-click a signal.
Editions
Free
Free for personal and commercial use
- Designs of up to 20,000 instances
- Hierarchy, Signals window and tracing
- Compile, elaborate and re-elaborate
- VCD and FST waveforms
Teven Pro coming soon
Everything in Free, plus
- No design size limit: open full chips
- Drag signals and instances from the design into the waveform
- Jump from a waveform signal to the logic that drives it
- Black boxes for tracing: stop traces at clock muxes, synchronisers and other cells
Every user will get a free 30-day Pro trial.
Questions
Which computers does it run on?
macOS on Apple silicon (M1 or newer), with VS Code 1.75 or newer. Linux and Windows versions are planned.
Do I need Python, a simulator or anything else?
No. Everything Teven uses is inside the extension.
Which languages and file formats does it read?
Verilog and SystemVerilog source, filelists (.f, with -f,
+incdir+ and +define+), and VCD and FST waveform dumps.
My design is bigger than 20,000 instances. What can I do?
Open a sub-block: elaborate with a lower top module. Teven Pro, coming soon, removes the limit.
VS Code asks whether I trust the publisher. Is that normal?
Yes. VS Code asks this the first time you install an extension from any new publisher. The publisher of Teven is InDrik Systems.
Support
Questions, bugs or ideas: write to support@indriksystems.com. For a problem, please include the Teven version and the text of View → Output → Teven in VS Code.